Call for Designs


The design rules for CORNERSTONE multi project wafer (MPW) run 9 on the 500 nm Si / 3 µm BOX SOI platform have been announced. We will offer 2 Si etch processes: 1) a shallow Si etch of 160 nm (grating couplers), and 2) a partial Si etch of 300 nm (rib waveguides). We will also offer a 1 µm thick silicon dioxide top cladding layer.
Access to this run is free of charge for UK research institutes (funded by EPSRC). Overseas universities and industrial companies can access this run with the following cost options:
Design area: 11.47 mm x 4.9 mm = £5,000.
Design area: 5.5 mm x 4.9 mm = £3,500.

The full design rules and .gds mask template can be found on the CORNERSTONE website (
The mask submission deadline is Friday 30th November 2018.

For more information on future calls, visit the Schedule & Cost page (
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