Second CORNERSTONE fabrication call

As part of the EPSRC-funded CORNERSTONE project, research institutions are invited to submit mask designs (deadline Friday 30th June 2017) to the forthcoming Silicon Photonics Multi-Project Wafer (MPW) run. This service is offered free of charge to UK institutions, but non-UK submissions are also welcomed for a small charge: please contact This email address is being protected from spambots. You need JavaScript enabled to view it. for pricing details.

The platform for this call is 220 nm Silicon-on-Insulator (SOI) with two Si etch depths of 70 nm and 220 nm. There is also the option of metal heaters. For more information and full design rules, please refer to the CORNERSTONE 2nd Call Design Rules document. For any queries, please contact This email address is being protected from spambots. You need JavaScript enabled to view it.

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